Integrated circuits are often used for driving loads in a variety of applications including those in the automotive environment. Such automotive loads may include dashboard lights, fuel injectors, solenoids, motors and the like. To provide the maximum voltage across such loads, the loads or load driving circuitry are typically tied directly to the vehicle battery.
Integrated circuits that drive these automotive loads fall into two broad categories; low side drivers and high side drivers. Referring to FIG. 1, a prior art example of a low side driver circuit 10 is illustrated. Circuit 10 includes a load driving device 12, illustrated in FIG. 1 as a metal-oxide-semiconductor field effect transistor (MOSFET), having a control input or gate receiving a gate drive signal GD, an output or source connected to ground potential or VSS, and a signal input or drain connected to one end of a load 14. The opposite end of load 14 is connected to battery voltage V.sub.BAT. Within circuit 10, load driving device 12 is responsive to the gate drive signal GD to conduct a load current I.sub.L from V.sub.BAT through load 14, and through device 12 to ground potential VSS.
Referring to FIG. 2, a prior art example of a high side driver circuit 20 is illustrated. High side driver circuit 20 includes a load driving device 12, illustrated in FIG. 2 as a MOSFET, including a control input or gate receiving a gate drive signal GD, a signal input or drain connected to battery voltage V.sub.BAT and an output or source connected to one end of a load 14. The opposite end of load 14 is connected to ground potential or VSS. In operation, load driving device 12 is responsive to the gate drive signal GD to conduct current from V.sub.BAT, from the drain to the source of device 12, through load 14 and to ground potential VSS.
In either of these circuit configurations 10 or 20 shown in FIGS. 1 and 2, the load driving device 12 is typically an N-channel MOSFET having a low voltage drop from drain to source when activated. Within circuits 10 and 20 of FIGS. 1 and 2, the load driving device 12 is illustrated as a double diffusion metal-oxide-semiconductor, or DMOS, transistor wherein the structure of one known configuration of a DMOS transistor 12 is shown in cross section in FIG. 3. Referring to FIG. 3, the N channel DMOS transistor 12 includes a substrate 30, typically formed from a P- semiconductor material in which a n-type buried layer silicon material 32 is formed. A n-type epitaxial layer 34 is typically grown or otherwise deposited on top of the substrate 30 and buried layer 32 combination, and a p-type isolation region 36 is diffused or otherwise implanted about a portion of layer 34 and extends into substrate 30 to thereby define a n-type silicon pocket 34'. A p+ layer 38 is typically diffused or otherwise implanted into a portion of the isolation region 36 to thereby form a low resistance contact for metal layer 40 which is typically tied to ground potential or VSS.
Within n-type pocket 34', a deep N+ (DN+) region 42 is diffused or otherwise implanted into n-type pocket 34' and extends into the buried layer 32 to thereby form a low resistance path through pocket 34' to the buried layer 32. A n+ silicon layer is diffused or otherwise implanted into DN+ layer 42 to thereby form an ohmic contact to metal layer 46 which defines the drain of the n-channel MOSFET. A p-type silicon layer 50 is diffused or otherwise implanted into n-type pocket 34' and a p+ silicon layer 54 is diffused or otherwise implanted into p-type layer 50 to thereby provide an ohmic contact to a metal layer 56 which defines the source of MOSFET 12. A n+ silicon layer 52 is diffused or otherwise implanted into p-type layer 50 about p+ region 54 and an oxide gate 58 is grown or otherwise deposited over p-type layer 50 and overlapping n+ layer 52 and n-type pocket 34'. A polysilicon layer 60 is formed over gate oxide 58 and defines the gate of MOSFET 12. An oxide layer 48, typically silicon dioxide (SiO.sub.2) or silicon nitride (SiN.sub.3), is formed over the bare silicon regions to thereby protect device 12 and insulate the silicon layers from the metal layers 40, 46, 56 and polysilicon layer 60. In the operation of MOSFET 12, a suitable gate voltage GD applied to gate 60 which forms a n-type depletion layer near the surface of p-type region 50 between n+ region 52 and n-type pocket 34' to thereby provide a current conduction path between drain 46 and source 56, as is known in the art.
In the typical structure of the n-channel MOSFET 12 illustrated in FIG. 3, two current conduction paths are formed that are separate from the operation of the MOSFET 12 as just described. A first current conduction path is formed between p-type region 50 and n-type pocket 34' and defines a so-called body diode between source 56 and drain 46 as illustrated by diode Z1 in FIGS. 1 and 2, wherein diode Z1 is operable to conduct a current I.sub.Z1 from source 56 to drain 46 under certain negative battery or negative transient operating conditions as will be described in greater detail hereinafter. A second current path is defined between isolation region 36 and n-type pocket 34' and defines a second diode illustrated in FIGS. 1 and 2 as diode Z2, wherein diode Z2 is operable to conduct a current I.sub.Z2 from VSS 40 to the drain 46 of MOSFET 12 under certain negative battery or negative transient operating conditions as will be described in greater detail hereinafter.
The automotive environment offers many challenges when driving loads directly from the battery, including a reverse battery condition (e.g. -13.5 volts) and negative transients due to inductive switching of loads elsewhere in the vehicle. When using a n-channel MOSFET device such as device 12, diodes Z1 and Z2 are operable to conduct currents I.sub.Z1 and I.sub.Z2 respectively when this negative voltage is applied to the battery line. In the low side driver configuration illustrated in FIG. 1, the negative battery condition or other negative transients generally do not cause a catastrophic problem since the currents I.sub.Z1 and I.sub.Z2 flowing from VSS to V.sub.BAT are limited by the internal impedance of load 14. This current limiting function of load 14 is typically sufficient to protect MOSFET 12 from damage or destruction in the low side driver configuration of FIG. 1.
In the high side driver configuration illustrated in FIG. 2, however, the drain of the MOSFET 12 is coupled directly to ground potential VSS via diode Z2, wherein the drain of MOSFET 12 is connected directly to V.sub.BAT. Thus, under negative battery conditions or other negative transients, while current I.sub.Z1 is limited by the internal impedance of load 14, the current I.sub.Z2 is limited only by the impedance of diode Z2 which is typically very small. With such little resistance from VSS to V.sub.BAT through diode Z2, the value of I.sub.Z2 may accordingly become excessively large and potentially destructive. As a result of large I.sub.Z2 current values, MOSFET 12 may latch up, the bond wires to the integrated circuit may become fused open, electromigration of the metal layers in the vicinity of device 12 may occur, and/or heat generated by the conduction of I.sub.Z2 may become excessive and damage or otherwise destroy the silicon. In any event, allowing the substantially unlimited current I.sub.Z2 to flow under negative battery or negative transient conditions could result in catastrophic damage to MOSFET 12 and surrounding circuitry.
At least three techniques for addressing the foregoing problems associated with negative battery and negative transient conditions in a n-channel MOSFET are known. According to one known technique, MOSFET 12 may be physically separated from the control circuitry controlling device 12 so that device 12 does not share an isolation region 36 in common with that of the control circuit generating the gate drive signal GD. This technique eliminates diode Z2 but requires partitioning MOSFET 12 and any control circuitry into separate integrated circuits which may be cost prohibitive.
According to a second known technique for addressing the above problem, a PNP bipolar transistor may be used to replace MOSFET 12 in the high side driver circuit 20 of FIG. 2. This technique eliminates any current flow back to the V.sub.BAT terminal under negative battery conditions, but is expensive at the integrated circuit level since the area required for a PNP transistor is much larger than that required by MOSFET 12 for the same performance. The PNP transistor also has a large base current that would be pulled from the V.sub.BAT line under normal operating conditions, thereby resulting in undesirable power dissipation and large quiescent currents.
A third known technique for addressing the above problem is to use a blocking diode between V.sub.BAT and the drain of MOSFET 12 to thereby block reverse current flow from the drain of MOSFET 12 to V.sub.BAT under reverse battery or negative transient conditions. Such blocking diodes, however, typically consume substantial circuit or circuit board space when sized large enough to handle the reverse voltage conditions as well as the load currents present during normal battery conditions. Moreover, the blocking diode creates a voltage drop in series with the load 14 that undesirably dissipates power and reduces the voltage across the load 14.
In an integrated circuit of the type illustrated in FIG. 3, the potential of isolation region 36 is preferably connected to the lowest potential on the integrated circuit in order to be effective as a device isolator on the circuit. Accordingly, isolation region 36 has been typically connected in the past to ground potential or VSS. Unfortunately, this common practice results in the potentially destructive flow of current I.sub.Z2 through diode z2 under negative battery or negative transient operating conditions in the high side driver configuration 20 illustrated in FIG. 2 as just described. What is therefore needed is a technique for addressing the problems associated with diode Z2 described hereinabove while also maintaining isolation region 36 at or near the lowest potential on the integrated circuit. By eliminating the potentially destructive current I.sub.Z2 and further providing for the connection of isolation region 36 to the lowest potential on the integrated circuit, such a technique would be ideally suited for applications wherein it would be desirable to form one or more MOSFETS 12 on the same integrated circuit as that of the control circuitry.